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B.TECH 5th sem Switching Theory and Logic Design paper 2017

UniversityGGSIPU, New Delhi
CourseB.TECH
Semester5
SubjectSwitching Theory and Logic Design
Year2017
Downloads23
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Sourabh Bajaj
200
 
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(a) What are universal gates? Design AND and OR gates using the universal gates.

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(b) State and prove the demorgan theorem.

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(c). Convert the following binary number of decimal numbers:

         (i) (101111.1101)2            (ii) (110101.101)2

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(a) Distinguish Melay and Moore machining.

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(e) What is the difference between conventional flow chart and ASM chart?

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(f) What are capabilities and limitations of finite state machines?

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 (g) What is the advantages of Master Slave FF.

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(a) Simply the expression Y =  (0,1,4,5, 6, 8, 9, 12, 13, 14) using the K-map.

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(b) Find the minimal sum of products for the Boolean expression:

f(w,x,y,z) =   (1,3,4,5,9,10,11) + d 6,8) using the Quine-Mccluskey method.

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(a) Design a 4-Bit magnitude comparator.

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(b) Design and explain the octal to binary encoder.

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(a) Design and explain the operation of TTL NOR gate. 

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(b) What are the advantages of CMOS logic? Discuss.

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(a) Design a synchronous MOD-10 counter.

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(6) What are the different type of shift registers? Explain.

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Design a sequence detector that produces an output '1' whenever the non overlapping sequence 1011 is detected. 

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Draw the merger graph and obtain the set of maximal compatibles for theincompletely specified sequential machine whose state table is given below:

                     

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Write short note on:

(a) Homing experiment

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(b) Fault models

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For the state diagram of the control circuit shown below:

(b) Design the circuit using multiplexers.

   

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For the state diagram of the control circuit shown below:

(a) Obtain the ASM chart.

         

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