VLSI Design

a). Explain the fabrication steps of CMOS inverter in p-well CMOS technology.

b) Draw the circuit of function  using

i) Transmission Gate

ii) Pseudo Logic

b} Explain CMOS logic based NAND SR latch circuit and explain its working. 

b) Describe the operation of basic MOS inverter. Derive the expression for pull-up to pull down ratio for a CMOS inverter.

a) Explain the MOS structure with N-type substrate in Accumulation,Depletion and inversion regions with the help of energy band diagram. 

b) Find the threshold voltage and body factory  for a N-channel transistor with n+ silicon gate if t_or 200 A^O, NA=3x 10%/cm, gate doping N_U=4x10¹⁹/cm³ and positively charged ions at the oxide silicon interface per unit area is 10¹⁰/cm2, T=300 K.

a) Obtain equation of delay  for CMOS inverter driving load  C_L . 

b) Draw the stick diagram of i) X-NOR Gate  ii) 2:1 MUX.

a) Design the circuit described by the function using CMOS logic. Also find the equivalent CMOS inverter circuit if (W/L)_p=10 and (W/L)n=5.

a) Draw and explain negative edge triggered D flip flop and verify it.

a) Explain the advantages of dynamic logic circuit over static logic circuit.Explain Domino and NORA CMOS logic circuit with suitable example. 

b) Draw and explain TSPC-based negative edge triggered DFF.

a) Discuss the hierarchy of various semiconductor technologies with Moorey'slaw and VLSI design flow (Y chart).

b) Explain the following circuits

.i) Variable threshold CMOS circuit

ii) Multiple threshold CMOS circuit 

Short note:

a) MOSFET Scaling

Short note:

b) Concept of regularity, Modularity and Locality

a) Explain MOSFET capacitance model with the help of suitable diagram. 

b) Draw and explain the layout of CMOS inverter, follow all  based rules.

C) Explain body effect and flat band voltage with the help of suitable diagrams.

d) Discuss how charge sharing problem can be avoided in dynamic CMOS logicstyle.

e) Explain why substrate and well contacts are important in CMOS.