Fundamentals Of HDL

a. Explain the following syntax with examples:

i) Procedure;

a. Describe VHDL scalar data types with an example,

b. Explain composite and access data types with an example for each.

c. If A, B and C are three unsigned variables with A=1C 0000 0000 find the value of i) A NAND B    ii) A&&Ç     iii) A ror2     iv) B<<I. 

a. Write a VHDL code in data flow description for a 26 magnitude comparator with help of truth table and simplified Boolean expressions. 

 b. Write a HDL codes for 2 x 2 bit combinational array multiplier (Both VHDL arid verilog). 

a. Write behavioral description of a half-adder in VHDL and verilog with propagation delay of 10ns. Discuss the important features of their description in VHDL and verilog.

b. Mention the names of sequential statements associated with behavioral description.

c. Write VHDL code for a D latch using variable assignment statement and signal assignment statements. With simulation Waveforms clearly distinguish between the two statements.

4. Explain with suitable examples, how binding is achieved in VHDL between

i) Entity and architecture

ii) Entity utd component

iii) Library and module.

b. Write a structural description using VHDL to implement a 2:1 multiplexer with active low enable.

c. Explain the use of generate statement. Write down format for it both in VHDL and verilog.

Write VHDL code for signal assignment statement Y = 2* x+3. Show the synthesized logic symbol and gate level diagram. Write structural code in verilog using gate level diagram.

a. Explain the following syntax with examples:

ii) Task;

a. Explain the following syntax with examples:

iii) Function

b. Write verilog description to convert signed binary to the integer using task.

c. Write a VHDL function to find the greater of two signed numbers.

a. Describe procedure for invoking a VHDL entity from a verilog module and a verilog module from a VHDL module. 

b. Develop mixed-language description of a 9 bit adder.

c. Write note on VHDL packages.

a. What is the necessity of mixed type description?

b. Describe the development of HDL code for an ALU and write VHDL/verilog code for ALU shown below.

(b) Assume the following operations: Addition, multiplieflon, division, no operation. 

a. What is synthesis? List the general steps involved in synthesis. 

 b. Write VHDL code for signal assignment statement Y =2*x+3. Show the synthesized logic symbol and gate level diagram. Write structural code in verilog using gate level diagram. 

Explain the use of generate statement. Write down format for it both in VHDL and verilog.

Explain composite and access data types with an example for each.

If A, B and C are three unsigned variables with A =1130000, B = 01011101 and C=00000000 find the value of   i) A NAND   ii) A&&Ç  iii)A ror2  iv) B<<I.

Write a VHDL code in data flow description for a bit magnitude comparator with help of truth table and simplified Boolean expressions. 

Write a HDL codes for 2 x 2 bit combinational array multiplier (Both VHDL and verilog). 

Write behavioral description of a half adder in VHDL and verilog with propagation delay of 10ns. Discuss the important features their description in VHDL and verilog.

Mention the names of sequential statements associated with behavioral description. 

Write VHDL code for a D latch using variable assignment statement and signal assignment statements. With simulatih Waveforms clearly distinguish between the two statements.

Explain with suitable examples, how binding is achieved in VHDL between

i) Entity and architecture 

Explain with suitable examples, how binding is achieved in VHDL between

ii) Entity and component 

Explain with suitable examples, how binding is achieved in VHDL between

iii) Library and module.

Write  structural description using VHDL to implement a 2:1 multiplexer with active low enable.

Describe VHDL scalar data types with an example.

Explain the following syntax with examples:

i) Procedure

Explain the following syntax with examples:

ii) Task;

Explain the following syntax with examples:

iii) Function

Write verilog description to convert signed binary to the integer using task.

Write a VHDL function to find the greater of two signed numbers.

Describe procedure for invoking a VHDL entity from a verilog module and a verilog module from a VHDL module.

Develop mixed-language description of a 9 bit adder.

Write note on VHDL packages.

a. What is the necessity of mixed type description?

Describe the development of HDL code for an ALU and write VHDL/verilog code for ALU shown below.

Assume the following operations: Addition, multiplication, division, no operation. 

What is synthesis? List the general steps involved in synthesis.